Why are wafer edges beveled

This can cause blisters to form and these blisters can continue to grow further through thermal expansion. If the blisters are broken by wafer handling, additional particles can be created. Wet etch processes can also attack the thin surfaces on the wafer edge, resulting in delamination that creates more particles.

This is a severe defect since these particles can potentially land on the center of the wafer and increase yield loss [4]. Peeling can also occur in 3D NAND as the carbon deposition, especially with memory hole and staircase patterning, is very thick and has potential to break off and become a peeling source. Arcing is the electrical breakdown of a gas that produces a prolonged electrical discharge.

There are process steps that require reactive ion etching and tungsten W fill where arcing can occur. The problem of arcing or electrical discharge of the plasma is particularly noticeable in RIE processes. Arcing damage can occur due to unequal charge distribution in low dielectric insulating layers during high aspect ratio RIE. The arcing damage tends to occur near metallization lines, which act as a ground path to charged areas in the dielectric insulating layer. Multiple layers of thin interlayer dielectric ILD , metal barrier TiN and conductor films W can form at the wafer edge with different thicknesses due to incomplete removal of residual particles.

These residual particles create undesirable interfaces between different materials at varying locations on the wafer, causing a charge buildup at the metallic interfaces where metal can be explosively vaporized [5]. This charge buildup leads to the ejection of metallic particles from the bevel area into the active area of the wafer, causing different types of shorts and significantly impacting yield.

Therefore, a proper bevel etch is needed after metal deposition to remove any future possibility of destructive arcing during RIE. In addition, the carbon hardmask used in 3D NAND is conductive and should be removed as it can also be an arcing source. These defects occur at the bevel region, if the etched material is exposed at the bevel during the etch process. In floating gate OPOP Oxide-Poly Si-Oxide-Poly Si gate first integration, the memory hole etch is non-selective to substrate and severe micromasking at the bevel region can occur during the memory hole and slit etch.

Micromasking at the bevel can be mitigated by carefully applying a bevel etch step, to prevent it from occurring at the oxide-nitride layer. During ONON integration, the nitride is removed and subsequently replaced with tungsten. When the same immersion exposure was used, significantly fewer edge flakes were detected in the near top region for Resist B and C than for Resist A Fig. Moreover, the residual defects were less confined to the exposure zone, so some of these defects might be caused by coating and wafer handling.

In the TopScan images, no clear sign of damage was seen. Clearly the choice of resist chemistry can be important to prevent these kinds of defects. As indicated earlier, resist residues can be optimized by changing the EBR recipe on the coat track. Resist A showed several hundred defect flakes with the regular short EBR sequence. After optimization, this resist achieved defect values similar to the background values obtained with the non-flaking resists B and C.

Edge flake defects as a function of resist chemistry and EBR recipe. More kinds of defects besides the edge region flakes can be important in immersion litho. This section discusses other possible defect sources. A variety of artifacts were seen even in fresh Si wafers, primarily on the bevel and apex region.

This introduces an additional concern with transport-related artifacts, and illustrates the need for an assessment of wafer edge quality and handling before introduction to the immersion process. At IMEC, resist work is typically done by a combination of a dry ashing step, followed by a wet clean.

In some cases, rework may be indicated to address an out-of-spec condition. Limited rework typically results in an increased presence of scratches typically at the lower bottom bevel , and an overall increase in reflectivity variation, indicating degraded surface quality. These defects could pose a risk when the immersion hood is passing over the wafer.

In this paper, we investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to inspection of the flat top part of the wafer edge due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution.

Our study used a new automated edge inspection system that provides full wafer edge imaging and automatic defect classification. The work revealed several key challenges to controlling wafer edge-related defectivity, including choice of resist, optimization of EBR recipes, and wafer handling. Licensee IntechOpen. Help us write another book on this subject and reach those readers.

Login to your personal dashboard for more detailed statistics on your publications. Edited by Michael Wang. We are IntechOpen, the world's leading publisher of Open Access books. Built by scientists, for scientists. Our readership spans scientists, professors, researchers, librarians, and students, as well as business professionals. Jami, I. Pollentier, S.

Vedula and G. Downloaded: Introduction In semiconductor manufacturing, the control of defects at the edge of the wafer is a key factor to keep the number of yielding die as high as possible per wafer. Wafer handling marks and resist rework process A variety of artifacts were seen even in fresh Si wafers, primarily on the bevel and apex region. Resist rework processes At IMEC, resist work is typically done by a combination of a dry ashing step, followed by a wet clean.

Conclusion In this paper, we investigated the impact of immersion lithography on wafer edge defectivity. More Print chapter. How to cite and reference Link to this chapter Copy to clipboard. Cite this chapter Copy to clipboard K. Blumenstock February 1st Site maintained and hosted by Freelock, LLC. Wafer Edge Grinding Services. MPE can also perform edge grinding on wafers which have been cored by an outside service.

Laser coring, waterjet, and dicing saw coring will all create wafers with straight edges and sharp corners. The wafers can be sent to MPE after coring to create a rounded or beveled edge profile. Small wafer diameter changes i. However, some diameter reduction may be necessary. MPE can bevel or round a sharp edge created on one side of a wafer after a thinning process. Edge grinding can be performed on either bare or fully processed silicon or SOI wafers with devices.